Binary file arch/arm/mach-msm/pm.o matches arch/arm/mach-msm/proc_comm.h: PCOM_VREG_SWITCH, arch/arm/mach-msm/proc_comm.h: PCOM_VREG_SET_LEVEL, arch/arm/mach-msm/proc_comm.h: PCOM_VREG_PULLDOWN, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_MSMA_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_MSMP_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_MSME1_ID, /* Not supported in Panoramix */ arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_MSMC1_ID, /* Not supported in PM6620 */ arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_MSMC2_ID, /* Supported in PM7500 only */ arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_GP3_ID, /* Supported in PM7500 only */ arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_MSME2_ID, /* Supported in PM7500 and Panoramix only */ arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_GP4_ID, /* Supported in PM7500 only */ arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_GP1_ID, /* Supported in PM7500 only */ arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_TCXO_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_PA_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_RFTX_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_RFRX1_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_RFRX2_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_SYNT_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_WLAN_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_USB_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_MMC_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_RUIM_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_MSMC0_ID, /* Supported in PM6610 only */ arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_GP2_ID, /* Supported in PM7500 only */ arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_GP5_ID, /* Supported in PM7500 only */ arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_GP6_ID, /* Supported in PM7500 only */ arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_RF_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_RF_VCO_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_MPLL_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_S2_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_S3_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_RFUBM_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_RF1_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_RF2_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_RFA_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_CDC2_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_RFTX2_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_USIM_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_USB2P6_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_USB3P3_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_INVALID_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_CAM_ID = PM_VREG_PDOWN_GP1_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_MDDI_ID = PM_VREG_PDOWN_GP2_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_RUIM2_ID = PM_VREG_PDOWN_GP3_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_AUX_ID = PM_VREG_PDOWN_GP4_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_AUX2_ID = PM_VREG_PDOWN_GP5_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_BT_ID = PM_VREG_PDOWN_GP6_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_MSME_ID = PM_VREG_PDOWN_MSME1_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_MSMC_ID = PM_VREG_PDOWN_MSMC1_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_RFA1_ID = PM_VREG_PDOWN_RFRX2_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_RFA2_ID = PM_VREG_PDOWN_RFTX2_ID, arch/arm/mach-msm/proc_comm.h: PM_VREG_PDOWN_XO_ID = PM_VREG_PDOWN_TCXO_ID arch/arm/mach-msm/proc_comm.h:} pm_vreg_pdown_id_type; Binary file arch/arm/mach-msm/smd.o matches Binary file arch/arm/mach-msm/vreg.o matches arch/arm/mach-msm/vreg.c:struct vreg *vreg_get(struct device *dev, const char *id) arch/arm/mach-msm/vreg.c:void vreg_put(struct vreg *vreg) arch/arm/mach-msm/vreg.c:int vreg_enable(struct vreg *vreg) arch/arm/mach-msm/vreg.c: return msm_proc_comm(PCOM_VREG_SWITCH, &id, &enable); arch/arm/mach-msm/vreg.c:void vreg_disable(struct vreg *vreg) arch/arm/mach-msm/vreg.c: msm_proc_comm(PCOM_VREG_SWITCH, &id, &enable); arch/arm/mach-msm/vreg.c:int vreg_set_level(struct vreg *vreg, unsigned mv) arch/arm/mach-msm/vreg.c: return msm_proc_comm(PCOM_VREG_SET_LEVEL, &id, &mv); arch/arm/mach-msm/vreg.c:static int vreg_debug_set(void *data, u64 val) arch/arm/mach-msm/vreg.c: vreg_disable(vreg); arch/arm/mach-msm/vreg.c: vreg_enable(vreg); arch/arm/mach-msm/vreg.c: vreg_set_level(vreg, val); arch/arm/mach-msm/vreg.c:static int vreg_debug_get(void *data, u64 *val) arch/arm/mach-msm/vreg.c:DEFINE_SIMPLE_ATTRIBUTE(vreg_fops, vreg_debug_get, vreg_debug_set, "%llu\n"); arch/arm/mach-msm/vreg.c:static int __init vreg_debug_init(void) arch/arm/mach-msm/vreg.c: debugfs_create_file(vregs[n].name, 0644, dent, vregs + n, &vreg_fops); arch/arm/mach-msm/vreg.c:device_initcall(vreg_debug_init); arch/arm/mach-msm/board-trout-panel.c:static struct vreg *vreg_mddi_1v5; arch/arm/mach-msm/board-trout-panel.c:static struct vreg *vreg_lcm_2v85; arch/arm/mach-msm/board-trout-panel.c: id = PM_VREG_PDOWN_MDDI_ID; arch/arm/mach-msm/board-trout-panel.c: msm_proc_comm(PCOM_VREG_PULLDOWN, &on_off, &id); arch/arm/mach-msm/board-trout-panel.c: vreg_enable(vreg_mddi_1v5); arch/arm/mach-msm/board-trout-panel.c: id = PM_VREG_PDOWN_AUX_ID; arch/arm/mach-msm/board-trout-panel.c: msm_proc_comm(PCOM_VREG_PULLDOWN, &on_off, &id); arch/arm/mach-msm/board-trout-panel.c: vreg_enable(vreg_lcm_2v85); arch/arm/mach-msm/board-trout-panel.c: vreg_disable(vreg_lcm_2v85); arch/arm/mach-msm/board-trout-panel.c: id = PM_VREG_PDOWN_AUX_ID; arch/arm/mach-msm/board-trout-panel.c: msm_proc_comm(PCOM_VREG_PULLDOWN, &on_off, &id); arch/arm/mach-msm/board-trout-panel.c: vreg_disable(vreg_mddi_1v5); arch/arm/mach-msm/board-trout-panel.c: id = PM_VREG_PDOWN_MDDI_ID; arch/arm/mach-msm/board-trout-panel.c: msm_proc_comm(PCOM_VREG_PULLDOWN, &on_off, &id); arch/arm/mach-msm/board-trout-panel.c: vreg_mddi_1v5 = vreg_get(0, "gp2"); arch/arm/mach-msm/board-trout-panel.c: if (IS_ERR(vreg_mddi_1v5)) arch/arm/mach-msm/board-trout-panel.c: return PTR_ERR(vreg_mddi_1v5); arch/arm/mach-msm/board-trout-panel.c: vreg_lcm_2v85 = vreg_get(0, "gp4"); arch/arm/mach-msm/board-trout-panel.c: if (IS_ERR(vreg_lcm_2v85)) arch/arm/mach-msm/board-trout-panel.c: return PTR_ERR(vreg_lcm_2v85); Binary file arch/arm/mach-msm/board-htcdiamond.o matches arch/arm/mach-msm/board-htcdiamond.c: struct vreg *vreg_mmc; arch/arm/mach-msm/board-htcdiamond.c: vreg_mmc = vreg_get(0, "mmc"); arch/arm/mach-msm/board-htcdiamond.c: rc = vreg_enable(vreg_mmc); Binary file arch/arm/mach-msm/proc_comm.o matches arch/arm/mach-msm/board-halibut.c: struct vreg *vreg_mmc; arch/arm/mach-msm/board-halibut.c: vreg_mmc = vreg_get(0, "mmc"); arch/arm/mach-msm/board-halibut.c: rc = vreg_enable(vreg_mmc); Binary file arch/arm/mach-msm/board-htcraphael.o matches arch/arm/mach-msm/board-htcraphael.c: struct vreg *vreg_mmc; arch/arm/mach-msm/board-htcraphael.c: vreg_mmc = vreg_get(0, "mmc"); arch/arm/mach-msm/board-htcraphael.c: rc = vreg_enable(vreg_mmc); arch/arm/mach-msm/board-trout-mmc.c:static struct vreg *vreg_sdslot; /* SD slot power */ arch/arm/mach-msm/board-trout-mmc.c:static unsigned int sdslot_vreg_enabled; arch/arm/mach-msm/board-trout-mmc.c: BUG_ON(!vreg_sdslot); arch/arm/mach-msm/board-trout-mmc.c: vreg_disable(vreg_sdslot); arch/arm/mach-msm/board-trout-mmc.c: sdslot_vreg_enabled = 0; arch/arm/mach-msm/board-trout-mmc.c: if (!sdslot_vreg_enabled) { arch/arm/mach-msm/board-trout-mmc.c: vreg_enable(vreg_sdslot); arch/arm/mach-msm/board-trout-mmc.c: sdslot_vreg_enabled = 1; arch/arm/mach-msm/board-trout-mmc.c: vreg_set_level(vreg_sdslot, mmc_vdd_table[i].level); arch/arm/mach-msm/board-trout-mmc.c:static struct vreg *vreg_wifi_osc; /* WIFI 32khz oscilator */ arch/arm/mach-msm/board-trout-mmc.c: rc = vreg_enable(vreg_wifi_osc); arch/arm/mach-msm/board-trout-mmc.c: vreg_disable(vreg_wifi_osc); arch/arm/mach-msm/board-trout-mmc.c: sdslot_vreg_enabled = 0; arch/arm/mach-msm/board-trout-mmc.c: vreg_sdslot = vreg_get(0, "gp6"); arch/arm/mach-msm/board-trout-mmc.c: if (IS_ERR(vreg_sdslot)) arch/arm/mach-msm/board-trout-mmc.c: return PTR_ERR(vreg_sdslot); arch/arm/mach-msm/board-trout-mmc.c: vreg_wifi_osc = vreg_get(0, "mmc"); arch/arm/mach-msm/board-trout-mmc.c: if (IS_ERR(vreg_wifi_osc)) arch/arm/mach-msm/board-trout-mmc.c: return PTR_ERR(vreg_wifi_osc); drivers/video/riva/nvreg.h:#ifndef __NVREG_H_ drivers/video/riva/nvreg.h:#define __NVREG_H_ drivers/video/sis/vstruct.h: const struct SiS_CHTVRegData *SiS_CHTVReg_UNTSC; drivers/video/sis/vstruct.h: const struct SiS_CHTVRegData *SiS_CHTVReg_ONTSC; drivers/video/sis/vstruct.h: const struct SiS_CHTVRegData *SiS_CHTVReg_UPAL; drivers/video/sis/vstruct.h: const struct SiS_CHTVRegData *SiS_CHTVReg_OPAL; drivers/video/sis/vstruct.h: const struct SiS_CHTVRegData *SiS_CHTVReg_UPALM; drivers/video/sis/vstruct.h: const struct SiS_CHTVRegData *SiS_CHTVReg_OPALM; drivers/video/sis/vstruct.h: const struct SiS_CHTVRegData *SiS_CHTVReg_UPALN; drivers/video/sis/vstruct.h: const struct SiS_CHTVRegData *SiS_CHTVReg_OPALN; drivers/video/sis/vstruct.h: const struct SiS_CHTVRegData *SiS_CHTVReg_SOPAL; drivers/video/sis/init301.c: case 0: CHTVRegData = SiS_Pr->SiS_CHTVReg_UNTSC; break; drivers/video/sis/init301.c: case 1: CHTVRegData = SiS_Pr->SiS_CHTVReg_ONTSC; break; drivers/video/sis/init301.c: case 2: CHTVRegData = SiS_Pr->SiS_CHTVReg_UPAL; break; drivers/video/sis/init301.c: case 3: CHTVRegData = SiS_Pr->SiS_CHTVReg_OPAL; break; drivers/video/sis/init301.c: case 4: CHTVRegData = SiS_Pr->SiS_CHTVReg_UPALM; break; drivers/video/sis/init301.c: case 5: CHTVRegData = SiS_Pr->SiS_CHTVReg_OPALM; break; drivers/video/sis/init301.c: case 6: CHTVRegData = SiS_Pr->SiS_CHTVReg_UPALN; break; drivers/video/sis/init301.c: case 7: CHTVRegData = SiS_Pr->SiS_CHTVReg_OPALN; break; drivers/video/sis/init301.c: case 8: CHTVRegData = SiS_Pr->SiS_CHTVReg_SOPAL; break; drivers/video/sis/init301.c: default: CHTVRegData = SiS_Pr->SiS_CHTVReg_OPAL; break; drivers/video/sis/300vtbl.h:static const struct SiS_CHTVRegData SiS300_CHTVReg_UNTSC[] = drivers/video/sis/300vtbl.h:static const struct SiS_CHTVRegData SiS300_CHTVReg_ONTSC[] = drivers/video/sis/300vtbl.h:static const struct SiS_CHTVRegData SiS300_CHTVReg_UPAL[] = drivers/video/sis/300vtbl.h:static const struct SiS_CHTVRegData SiS300_CHTVReg_OPAL[] = drivers/video/sis/300vtbl.h:static const struct SiS_CHTVRegData SiS300_CHTVReg_SOPAL[] = drivers/video/sis/init.c: SiS_Pr->SiS_CHTVReg_UNTSC = SiS300_CHTVReg_UNTSC; drivers/video/sis/init.c: SiS_Pr->SiS_CHTVReg_ONTSC = SiS300_CHTVReg_ONTSC; drivers/video/sis/init.c: SiS_Pr->SiS_CHTVReg_UPAL = SiS300_CHTVReg_UPAL; drivers/video/sis/init.c: SiS_Pr->SiS_CHTVReg_OPAL = SiS300_CHTVReg_OPAL; drivers/video/sis/init.c: SiS_Pr->SiS_CHTVReg_UPALM = SiS300_CHTVReg_UNTSC; /* not supported on 300 series */ drivers/video/sis/init.c: SiS_Pr->SiS_CHTVReg_OPALM = SiS300_CHTVReg_ONTSC; /* not supported on 300 series */ drivers/video/sis/init.c: SiS_Pr->SiS_CHTVReg_UPALN = SiS300_CHTVReg_UPAL; /* not supported on 300 series */ drivers/video/sis/init.c: SiS_Pr->SiS_CHTVReg_OPALN = SiS300_CHTVReg_OPAL; /* not supported on 300 series */ drivers/video/sis/init.c: SiS_Pr->SiS_CHTVReg_SOPAL = SiS300_CHTVReg_SOPAL; drivers/video/sis/init.c: SiS_Pr->SiS_CHTVReg_UNTSC = SiS310_CHTVReg_UNTSC; drivers/video/sis/init.c: SiS_Pr->SiS_CHTVReg_ONTSC = SiS310_CHTVReg_ONTSC; drivers/video/sis/init.c: SiS_Pr->SiS_CHTVReg_UPAL = SiS310_CHTVReg_UPAL; drivers/video/sis/init.c: SiS_Pr->SiS_CHTVReg_OPAL = SiS310_CHTVReg_OPAL; drivers/video/sis/init.c: SiS_Pr->SiS_CHTVReg_UPALM = SiS310_CHTVReg_UPALM; drivers/video/sis/init.c: SiS_Pr->SiS_CHTVReg_OPALM = SiS310_CHTVReg_OPALM; drivers/video/sis/init.c: SiS_Pr->SiS_CHTVReg_UPALN = SiS310_CHTVReg_UPALN; drivers/video/sis/init.c: SiS_Pr->SiS_CHTVReg_OPALN = SiS310_CHTVReg_OPALN; drivers/video/sis/init.c: SiS_Pr->SiS_CHTVReg_SOPAL = SiS310_CHTVReg_OPAL; drivers/video/sis/310vtbl.h:static const struct SiS_CHTVRegData SiS310_CHTVReg_UNTSC[] = drivers/video/sis/310vtbl.h:static const struct SiS_CHTVRegData SiS310_CHTVReg_ONTSC[] = drivers/video/sis/310vtbl.h:static const struct SiS_CHTVRegData SiS310_CHTVReg_UPAL[] = drivers/video/sis/310vtbl.h:static const struct SiS_CHTVRegData SiS310_CHTVReg_OPAL[] = drivers/video/sis/310vtbl.h:static const struct SiS_CHTVRegData SiS310_CHTVReg_UPALM[] = drivers/video/sis/310vtbl.h:static const struct SiS_CHTVRegData SiS310_CHTVReg_OPALM[] = drivers/video/sis/310vtbl.h:static const struct SiS_CHTVRegData SiS310_CHTVReg_UPALN[] = drivers/video/sis/310vtbl.h:static const struct SiS_CHTVRegData SiS310_CHTVReg_OPALN[] = drivers/net/forcedeth.c: * interrupt fires (100 times/second, configurable with NVREG_POLL_DEFAULT) drivers/net/forcedeth.c:#define NVREG_IRQSTAT_MIIEVENT 0x040 drivers/net/forcedeth.c:#define NVREG_IRQSTAT_MASK 0x81ff drivers/net/forcedeth.c:#define NVREG_IRQ_RX_ERROR 0x0001 drivers/net/forcedeth.c:#define NVREG_IRQ_RX 0x0002 drivers/net/forcedeth.c:#define NVREG_IRQ_RX_NOBUF 0x0004 drivers/net/forcedeth.c:#define NVREG_IRQ_TX_ERR 0x0008 drivers/net/forcedeth.c:#define NVREG_IRQ_TX_OK 0x0010 drivers/net/forcedeth.c:#define NVREG_IRQ_TIMER 0x0020 drivers/net/forcedeth.c:#define NVREG_IRQ_LINK 0x0040 drivers/net/forcedeth.c:#define NVREG_IRQ_RX_FORCED 0x0080 drivers/net/forcedeth.c:#define NVREG_IRQ_TX_FORCED 0x0100 drivers/net/forcedeth.c:#define NVREG_IRQ_RECOVER_ERROR 0x8000 drivers/net/forcedeth.c:#define NVREG_IRQMASK_THROUGHPUT 0x00df drivers/net/forcedeth.c:#define NVREG_IRQMASK_CPU 0x0060 drivers/net/forcedeth.c:#define NVREG_IRQ_TX_ALL (NVREG_IRQ_TX_ERR|NVREG_IRQ_TX_OK|NVREG_IRQ_TX_FORCED) drivers/net/forcedeth.c:#define NVREG_IRQ_RX_ALL (NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_RX_FORCED) drivers/net/forcedeth.c:#define NVREG_IRQ_OTHER (NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RECOVER_ERROR) drivers/net/forcedeth.c:#define NVREG_IRQ_UNKNOWN (~(NVREG_IRQ_RX_ERROR|NVREG_IRQ_RX|NVREG_IRQ_RX_NOBUF|NVREG_IRQ_TX_ERR| \ drivers/net/forcedeth.c: NVREG_IRQ_TX_OK|NVREG_IRQ_TIMER|NVREG_IRQ_LINK|NVREG_IRQ_RX_FORCED| \ drivers/net/forcedeth.c: NVREG_IRQ_TX_FORCED|NVREG_IRQ_RECOVER_ERROR)) drivers/net/forcedeth.c:#define NVREG_UNKSETUP6_VAL 3 drivers/net/forcedeth.c: * NVREG_POLL_DEFAULT is the interval length of the timer source on the nic drivers/net/forcedeth.c: * NVREG_POLL_DEFAULT=97 would result in an interval length of 1 ms drivers/net/forcedeth.c:#define NVREG_POLL_DEFAULT_THROUGHPUT 970 /* backup tx cleanup if loop max reached */ drivers/net/forcedeth.c:#define NVREG_POLL_DEFAULT_CPU 13 drivers/net/forcedeth.c:#define NVREG_MSI_VECTOR_0_ENABLED 0x01 drivers/net/forcedeth.c:#define NVREG_MISC1_PAUSE_TX 0x01 drivers/net/forcedeth.c:#define NVREG_MISC1_HD 0x02 drivers/net/forcedeth.c:#define NVREG_MISC1_FORCE 0x3b0f3c drivers/net/forcedeth.c:#define NVREG_MAC_RESET_ASSERT 0x0F3 drivers/net/forcedeth.c:#define NVREG_XMITCTL_START 0x01 drivers/net/forcedeth.c:#define NVREG_XMITCTL_MGMT_ST 0x40000000 drivers/net/forcedeth.c:#define NVREG_XMITCTL_SYNC_MASK 0x000f0000 drivers/net/forcedeth.c:#define NVREG_XMITCTL_SYNC_NOT_READY 0x0 drivers/net/forcedeth.c:#define NVREG_XMITCTL_SYNC_PHY_INIT 0x00040000 drivers/net/forcedeth.c:#define NVREG_XMITCTL_MGMT_SEMA_MASK 0x00000f00 drivers/net/forcedeth.c:#define NVREG_XMITCTL_MGMT_SEMA_FREE 0x0 drivers/net/forcedeth.c:#define NVREG_XMITCTL_HOST_SEMA_MASK 0x0000f000 drivers/net/forcedeth.c:#define NVREG_XMITCTL_HOST_SEMA_ACQ 0x0000f000 drivers/net/forcedeth.c:#define NVREG_XMITCTL_HOST_LOADED 0x00004000 drivers/net/forcedeth.c:#define NVREG_XMITCTL_TX_PATH_EN 0x01000000 drivers/net/forcedeth.c:#define NVREG_XMITSTAT_BUSY 0x01 drivers/net/forcedeth.c:#define NVREG_PFF_PAUSE_RX 0x08 drivers/net/forcedeth.c:#define NVREG_PFF_ALWAYS 0x7F0000 drivers/net/forcedeth.c:#define NVREG_PFF_PROMISC 0x80 drivers/net/forcedeth.c:#define NVREG_PFF_MYADDR 0x20 drivers/net/forcedeth.c:#define NVREG_PFF_LOOPBACK 0x10 drivers/net/forcedeth.c:#define NVREG_OFFLOAD_HOMEPHY 0x601 drivers/net/forcedeth.c:#define NVREG_OFFLOAD_NORMAL RX_NIC_BUFSIZE drivers/net/forcedeth.c:#define NVREG_RCVCTL_START 0x01 drivers/net/forcedeth.c:#define NVREG_RCVCTL_RX_PATH_EN 0x01000000 drivers/net/forcedeth.c:#define NVREG_RCVSTAT_BUSY 0x01 drivers/net/forcedeth.c:#define NVREG_RNDSEED_MASK 0x00ff drivers/net/forcedeth.c:#define NVREG_RNDSEED_FORCE 0x7f00 drivers/net/forcedeth.c:#define NVREG_RNDSEED_FORCE2 0x2d00 drivers/net/forcedeth.c:#define NVREG_RNDSEED_FORCE3 0x7400 drivers/net/forcedeth.c:#define NVREG_TX_DEFERRAL_DEFAULT 0x15050f drivers/net/forcedeth.c:#define NVREG_TX_DEFERRAL_RGMII_10_100 0x16070f drivers/net/forcedeth.c:#define NVREG_TX_DEFERRAL_RGMII_1000 0x14050f drivers/net/forcedeth.c:#define NVREG_TX_DEFERRAL_RGMII_STRETCH_10 0x16190f drivers/net/forcedeth.c:#define NVREG_TX_DEFERRAL_RGMII_STRETCH_100 0x16300f drivers/net/forcedeth.c:#define NVREG_TX_DEFERRAL_MII_STRETCH 0x152000 drivers/net/forcedeth.c:#define NVREG_RX_DEFERRAL_DEFAULT 0x16 drivers/net/forcedeth.c:#define NVREG_MCASTADDRA_FORCE 0x01 drivers/net/forcedeth.c:#define NVREG_MCASTMASKA_NONE 0xffffffff drivers/net/forcedeth.c:#define NVREG_MCASTMASKB_NONE 0xffff drivers/net/forcedeth.c:#define NVREG_RINGSZ_TXSHIFT 0 drivers/net/forcedeth.c:#define NVREG_RINGSZ_RXSHIFT 16 drivers/net/forcedeth.c:#define NVREG_TRANSMITPOLL_MAC_ADDR_REV 0x00008000 drivers/net/forcedeth.c:#define NVREG_LINKSPEED_FORCE 0x10000 drivers/net/forcedeth.c:#define NVREG_LINKSPEED_10 1000 drivers/net/forcedeth.c:#define NVREG_LINKSPEED_100 100 drivers/net/forcedeth.c:#define NVREG_LINKSPEED_1000 50 drivers/net/forcedeth.c:#define NVREG_LINKSPEED_MASK (0xFFF) drivers/net/forcedeth.c:#define NVREG_UNKSETUP5_BIT31 (1<<31) drivers/net/forcedeth.c:#define NVREG_TX_WM_DESC1_DEFAULT 0x0200010 drivers/net/forcedeth.c:#define NVREG_TX_WM_DESC2_3_DEFAULT 0x1e08000 drivers/net/forcedeth.c:#define NVREG_TX_WM_DESC2_3_1000 0xfe08000 drivers/net/forcedeth.c:#define NVREG_TXRXCTL_KICK 0x0001 drivers/net/forcedeth.c:#define NVREG_TXRXCTL_BIT1 0x0002 drivers/net/forcedeth.c:#define NVREG_TXRXCTL_BIT2 0x0004 drivers/net/forcedeth.c:#define NVREG_TXRXCTL_IDLE 0x0008 drivers/net/forcedeth.c:#define NVREG_TXRXCTL_RESET 0x0010 drivers/net/forcedeth.c:#define NVREG_TXRXCTL_RXCHECK 0x0400 drivers/net/forcedeth.c:#define NVREG_TXRXCTL_DESC_1 0 drivers/net/forcedeth.c:#define NVREG_TXRXCTL_DESC_2 0x002100 drivers/net/forcedeth.c:#define NVREG_TXRXCTL_DESC_3 0xc02200 drivers/net/forcedeth.c:#define NVREG_TXRXCTL_VLANSTRIP 0x00040 drivers/net/forcedeth.c:#define NVREG_TXRXCTL_VLANINS 0x00080 drivers/net/forcedeth.c:#define NVREG_TX_PAUSEFRAME_DISABLE 0x0fff0080 drivers/net/forcedeth.c:#define NVREG_TX_PAUSEFRAME_ENABLE_V1 0x01800010 drivers/net/forcedeth.c:#define NVREG_TX_PAUSEFRAME_ENABLE_V2 0x056003f0 drivers/net/forcedeth.c:#define NVREG_TX_PAUSEFRAME_ENABLE_V3 0x09f00880 drivers/net/forcedeth.c:#define NVREG_MIISTAT_ERROR 0x0001 drivers/net/forcedeth.c:#define NVREG_MIISTAT_LINKCHANGE 0x0008 drivers/net/forcedeth.c:#define NVREG_MIISTAT_MASK_RW 0x0007 drivers/net/forcedeth.c:#define NVREG_MIISTAT_MASK_ALL 0x000f drivers/net/forcedeth.c:#define NVREG_MII_LINKCHANGE 0x0008 drivers/net/forcedeth.c:#define NVREG_ADAPTCTL_START 0x02 drivers/net/forcedeth.c:#define NVREG_ADAPTCTL_LINKUP 0x04 drivers/net/forcedeth.c:#define NVREG_ADAPTCTL_PHYVALID 0x40000 drivers/net/forcedeth.c:#define NVREG_ADAPTCTL_RUNNING 0x100000 drivers/net/forcedeth.c:#define NVREG_ADAPTCTL_PHYSHIFT 24 drivers/net/forcedeth.c:#define NVREG_MIISPEED_BIT8 (1<<8) drivers/net/forcedeth.c:#define NVREG_MIIDELAY 5 drivers/net/forcedeth.c:#define NVREG_MIICTL_INUSE 0x08000 drivers/net/forcedeth.c:#define NVREG_MIICTL_WRITE 0x00400 drivers/net/forcedeth.c:#define NVREG_MIICTL_ADDRSHIFT 5 drivers/net/forcedeth.c:#define NVREG_WAKEUPFLAGS_VAL 0x7770 drivers/net/forcedeth.c:#define NVREG_WAKEUPFLAGS_BUSYSHIFT 24 drivers/net/forcedeth.c:#define NVREG_WAKEUPFLAGS_ENABLESHIFT 16 drivers/net/forcedeth.c:#define NVREG_WAKEUPFLAGS_D3SHIFT 12 drivers/net/forcedeth.c:#define NVREG_WAKEUPFLAGS_D2SHIFT 8 drivers/net/forcedeth.c:#define NVREG_WAKEUPFLAGS_D1SHIFT 4 drivers/net/forcedeth.c:#define NVREG_WAKEUPFLAGS_D0SHIFT 0 drivers/net/forcedeth.c:#define NVREG_WAKEUPFLAGS_ACCEPT_MAGPAT 0x01 drivers/net/forcedeth.c:#define NVREG_WAKEUPFLAGS_ACCEPT_WAKEUPPAT 0x02 drivers/net/forcedeth.c:#define NVREG_WAKEUPFLAGS_ACCEPT_LINKCHANGE 0x04 drivers/net/forcedeth.c:#define NVREG_WAKEUPFLAGS_ENABLE 0x1111 drivers/net/forcedeth.c:#define NVREG_POWERCAP_D3SUPP (1<<30) drivers/net/forcedeth.c:#define NVREG_POWERCAP_D2SUPP (1<<26) drivers/net/forcedeth.c:#define NVREG_POWERCAP_D1SUPP (1<<25) drivers/net/forcedeth.c:#define NVREG_POWERSTATE_POWEREDUP 0x8000 drivers/net/forcedeth.c:#define NVREG_POWERSTATE_VALID 0x0100 drivers/net/forcedeth.c:#define NVREG_POWERSTATE_MASK 0x0003 drivers/net/forcedeth.c:#define NVREG_POWERSTATE_D0 0x0000 drivers/net/forcedeth.c:#define NVREG_POWERSTATE_D1 0x0001 drivers/net/forcedeth.c:#define NVREG_POWERSTATE_D2 0x0002 drivers/net/forcedeth.c:#define NVREG_POWERSTATE_D3 0x0003 drivers/net/forcedeth.c:#define NVREG_VLANCONTROL_ENABLE 0x2000 drivers/net/forcedeth.c:#define NVREG_POWERSTATE2_POWERUP_MASK 0x0F11 drivers/net/forcedeth.c:#define NVREG_POWERSTATE2_POWERUP_REV_A3 0x0001 drivers/net/forcedeth.c: writel(NVREG_MIISTAT_MASK_RW, base + NvRegMIIStatus); drivers/net/forcedeth.c: if (reg & NVREG_MIICTL_INUSE) { drivers/net/forcedeth.c: writel(NVREG_MIICTL_INUSE, base + NvRegMIIControl); drivers/net/forcedeth.c: reg = (addr << NVREG_MIICTL_ADDRSHIFT) | miireg; drivers/net/forcedeth.c: reg |= NVREG_MIICTL_WRITE; drivers/net/forcedeth.c: if (reg_delay(dev, NvRegMIIControl, NVREG_MIICTL_INUSE, 0, drivers/net/forcedeth.c: } else if (readl(base + NvRegMIIStatus) & NVREG_MIISTAT_ERROR) { drivers/net/forcedeth.c: if ((readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) && !np->mac_in_use) { drivers/net/forcedeth.c: rx_ctrl &= ~NVREG_RCVCTL_START; drivers/net/forcedeth.c: rx_ctrl |= NVREG_RCVCTL_START; drivers/net/forcedeth.c: rx_ctrl &= ~NVREG_RCVCTL_RX_PATH_EN; drivers/net/forcedeth.c: rx_ctrl &= ~NVREG_RCVCTL_START; drivers/net/forcedeth.c: rx_ctrl |= NVREG_RCVCTL_RX_PATH_EN; drivers/net/forcedeth.c: reg_delay(dev, NvRegReceiverStatus, NVREG_RCVSTAT_BUSY, 0, drivers/net/forcedeth.c: tx_ctrl |= NVREG_XMITCTL_START; drivers/net/forcedeth.c: tx_ctrl &= ~NVREG_XMITCTL_TX_PATH_EN; drivers/net/forcedeth.c: tx_ctrl &= ~NVREG_XMITCTL_START; drivers/net/forcedeth.c: tx_ctrl |= NVREG_XMITCTL_TX_PATH_EN; drivers/net/forcedeth.c: reg_delay(dev, NvRegTransmitterStatus, NVREG_XMITSTAT_BUSY, 0, drivers/net/forcedeth.c: writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, drivers/net/forcedeth.c: writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); drivers/net/forcedeth.c: writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); drivers/net/forcedeth.c: writel(NVREG_TXRXCTL_BIT2 | NVREG_TXRXCTL_RESET | np->txrxctl_bits, base + NvRegTxRxControl); drivers/net/forcedeth.c: writel(NVREG_MAC_RESET_ASSERT, base + NvRegMacReset); drivers/net/forcedeth.c: writel(NVREG_TXRXCTL_BIT2 | np->txrxctl_bits, base + NvRegTxRxControl); drivers/net/forcedeth.c: writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); drivers/net/forcedeth.c: writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); drivers/net/forcedeth.c: writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); drivers/net/forcedeth.c: status = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; drivers/net/forcedeth.c: status = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; drivers/net/forcedeth.c: writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), drivers/net/forcedeth.c: writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); drivers/net/forcedeth.c: u32 pff = readl(base + NvRegPacketFilterFlags) & NVREG_PFF_PAUSE_RX; drivers/net/forcedeth.c: pff |= NVREG_PFF_PROMISC; drivers/net/forcedeth.c: pff |= NVREG_PFF_MYADDR; drivers/net/forcedeth.c: mask[0] = NVREG_MCASTMASKA_NONE; drivers/net/forcedeth.c: mask[1] = NVREG_MCASTMASKB_NONE; drivers/net/forcedeth.c: addr[0] |= NVREG_MCASTADDRA_FORCE; drivers/net/forcedeth.c: pff |= NVREG_PFF_ALWAYS; drivers/net/forcedeth.c: u32 pff = readl(base + NvRegPacketFilterFlags) & ~NVREG_PFF_PAUSE_RX; drivers/net/forcedeth.c: writel(pff|NVREG_PFF_PAUSE_RX, base + NvRegPacketFilterFlags); drivers/net/forcedeth.c: u32 regmisc = readl(base + NvRegMisc1) & ~NVREG_MISC1_PAUSE_TX; drivers/net/forcedeth.c: u32 pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V1; drivers/net/forcedeth.c: pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V2; drivers/net/forcedeth.c: pause_enable = NVREG_TX_PAUSEFRAME_ENABLE_V3; drivers/net/forcedeth.c: writel(regmisc|NVREG_MISC1_PAUSE_TX, base + NvRegMisc1); drivers/net/forcedeth.c: writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); drivers/net/forcedeth.c: newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; drivers/net/forcedeth.c: newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; drivers/net/forcedeth.c: newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; drivers/net/forcedeth.c: newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; drivers/net/forcedeth.c: newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; drivers/net/forcedeth.c: newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; drivers/net/forcedeth.c: newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_1000; drivers/net/forcedeth.c: newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; drivers/net/forcedeth.c: newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_100; drivers/net/forcedeth.c: newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; drivers/net/forcedeth.c: newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; drivers/net/forcedeth.c: newls = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; drivers/net/forcedeth.c: if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_START) { drivers/net/forcedeth.c: if (readl(base + NvRegReceiverControl) & NVREG_RCVCTL_START) { drivers/net/forcedeth.c: if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_10) drivers/net/forcedeth.c: phyreg |= NVREG_RNDSEED_FORCE3; drivers/net/forcedeth.c: else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_100) drivers/net/forcedeth.c: phyreg |= NVREG_RNDSEED_FORCE2; drivers/net/forcedeth.c: else if ((np->linkspeed & 0xFFF) == NVREG_LINKSPEED_1000) drivers/net/forcedeth.c: phyreg |= NVREG_RNDSEED_FORCE; drivers/net/forcedeth.c: if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_100) drivers/net/forcedeth.c: else if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) drivers/net/forcedeth.c: if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) { drivers/net/forcedeth.c: txreg = NVREG_TX_DEFERRAL_RGMII_1000; drivers/net/forcedeth.c: if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_10) drivers/net/forcedeth.c: txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_10; drivers/net/forcedeth.c: txreg = NVREG_TX_DEFERRAL_RGMII_STRETCH_100; drivers/net/forcedeth.c: txreg = NVREG_TX_DEFERRAL_RGMII_10_100; drivers/net/forcedeth.c: txreg = NVREG_TX_DEFERRAL_MII_STRETCH; drivers/net/forcedeth.c: txreg = NVREG_TX_DEFERRAL_DEFAULT; drivers/net/forcedeth.c: txreg = NVREG_TX_WM_DESC1_DEFAULT; drivers/net/forcedeth.c: if ((np->linkspeed & NVREG_LINKSPEED_MASK) == NVREG_LINKSPEED_1000) drivers/net/forcedeth.c: txreg = NVREG_TX_WM_DESC2_3_1000; drivers/net/forcedeth.c: txreg = NVREG_TX_WM_DESC2_3_DEFAULT; drivers/net/forcedeth.c: writel(NVREG_MISC1_FORCE | ( np->duplex ? 0 : NVREG_MISC1_HD), drivers/net/forcedeth.c: writel(NVREG_MIISTAT_LINKCHANGE, base + NvRegMIIStatus); drivers/net/forcedeth.c: if (miistat & (NVREG_MIISTAT_LINKCHANGE)) drivers/net/forcedeth.c: events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; drivers/net/forcedeth.c: writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); drivers/net/forcedeth.c: events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; drivers/net/forcedeth.c: writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); drivers/net/forcedeth.c: if (events & NVREG_IRQ_RX_ALL) { drivers/net/forcedeth.c: np->irqmask &= ~NVREG_IRQ_RX_ALL; drivers/net/forcedeth.c: writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); drivers/net/forcedeth.c: if (unlikely(events & NVREG_IRQ_LINK)) { drivers/net/forcedeth.c: if (unlikely(events & (NVREG_IRQ_TX_ERR))) { drivers/net/forcedeth.c: if (unlikely(events & (NVREG_IRQ_UNKNOWN))) { drivers/net/forcedeth.c: if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) { drivers/net/forcedeth.c: events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; drivers/net/forcedeth.c: writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); drivers/net/forcedeth.c: events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; drivers/net/forcedeth.c: writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); drivers/net/forcedeth.c: if (events & NVREG_IRQ_RX_ALL) { drivers/net/forcedeth.c: np->irqmask &= ~NVREG_IRQ_RX_ALL; drivers/net/forcedeth.c: writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); drivers/net/forcedeth.c: if (unlikely(events & NVREG_IRQ_LINK)) { drivers/net/forcedeth.c: if (unlikely(events & (NVREG_IRQ_TX_ERR))) { drivers/net/forcedeth.c: if (unlikely(events & (NVREG_IRQ_UNKNOWN))) { drivers/net/forcedeth.c: if (unlikely(events & NVREG_IRQ_RECOVER_ERROR)) { drivers/net/forcedeth.c: events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_TX_ALL; drivers/net/forcedeth.c: writel(NVREG_IRQ_TX_ALL, base + NvRegMSIXIrqStatus); drivers/net/forcedeth.c: if (unlikely(events & (NVREG_IRQ_TX_ERR))) { drivers/net/forcedeth.c: writel(NVREG_IRQ_TX_ALL, base + NvRegIrqMask); drivers/net/forcedeth.c: np->nic_poll_irq |= NVREG_IRQ_TX_ALL; drivers/net/forcedeth.c: np->irqmask |= NVREG_IRQ_RX_ALL; drivers/net/forcedeth.c: writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); drivers/net/forcedeth.c: events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL; drivers/net/forcedeth.c: writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus); drivers/net/forcedeth.c: writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); drivers/net/forcedeth.c: events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_RX_ALL; drivers/net/forcedeth.c: writel(NVREG_IRQ_RX_ALL, base + NvRegMSIXIrqStatus); drivers/net/forcedeth.c: writel(NVREG_IRQ_RX_ALL, base + NvRegIrqMask); drivers/net/forcedeth.c: np->nic_poll_irq |= NVREG_IRQ_RX_ALL; drivers/net/forcedeth.c: events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQ_OTHER; drivers/net/forcedeth.c: writel(NVREG_IRQ_OTHER, base + NvRegMSIXIrqStatus); drivers/net/forcedeth.c: if (events & NVREG_IRQ_LINK) { drivers/net/forcedeth.c: if (events & NVREG_IRQ_RECOVER_ERROR) { drivers/net/forcedeth.c: writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); drivers/net/forcedeth.c: np->nic_poll_irq |= NVREG_IRQ_OTHER; drivers/net/forcedeth.c: if (events & (NVREG_IRQ_UNKNOWN)) { drivers/net/forcedeth.c: writel(NVREG_IRQ_OTHER, base + NvRegIrqMask); drivers/net/forcedeth.c: np->nic_poll_irq |= NVREG_IRQ_OTHER; drivers/net/forcedeth.c: events = readl(base + NvRegIrqStatus) & NVREG_IRQSTAT_MASK; drivers/net/forcedeth.c: writel(NVREG_IRQ_TIMER, base + NvRegIrqStatus); drivers/net/forcedeth.c: events = readl(base + NvRegMSIXIrqStatus) & NVREG_IRQSTAT_MASK; drivers/net/forcedeth.c: writel(NVREG_IRQ_TIMER, base + NvRegMSIXIrqStatus); drivers/net/forcedeth.c: if (!(events & NVREG_IRQ_TIMER)) drivers/net/forcedeth.c: set_msix_vector_map(dev, NV_MSI_X_VECTOR_RX, NVREG_IRQ_RX_ALL); drivers/net/forcedeth.c: set_msix_vector_map(dev, NV_MSI_X_VECTOR_TX, NVREG_IRQ_TX_ALL); drivers/net/forcedeth.c: set_msix_vector_map(dev, NV_MSI_X_VECTOR_OTHER, NVREG_IRQ_OTHER); drivers/net/forcedeth.c: writel(NVREG_MSI_VECTOR_0_ENABLED, base + NvRegMSIIrqMask); drivers/net/forcedeth.c: if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { drivers/net/forcedeth.c: mask |= NVREG_IRQ_RX_ALL; drivers/net/forcedeth.c: if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { drivers/net/forcedeth.c: mask |= NVREG_IRQ_TX_ALL; drivers/net/forcedeth.c: if (np->nic_poll_irq & NVREG_IRQ_OTHER) { drivers/net/forcedeth.c: mask |= NVREG_IRQ_OTHER; drivers/net/forcedeth.c: writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), drivers/net/forcedeth.c: writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); drivers/net/forcedeth.c: if (np->nic_poll_irq & NVREG_IRQ_RX_ALL) { drivers/net/forcedeth.c: if (np->nic_poll_irq & NVREG_IRQ_TX_ALL) { drivers/net/forcedeth.c: if (np->nic_poll_irq & NVREG_IRQ_OTHER) { drivers/net/forcedeth.c: flags = NVREG_WAKEUPFLAGS_ENABLE; drivers/net/forcedeth.c: switch(np->linkspeed & (NVREG_LINKSPEED_MASK)) { drivers/net/forcedeth.c: case NVREG_LINKSPEED_10: drivers/net/forcedeth.c: case NVREG_LINKSPEED_100: drivers/net/forcedeth.c: case NVREG_LINKSPEED_1000: drivers/net/forcedeth.c: writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), drivers/net/forcedeth.c: writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); drivers/net/forcedeth.c: np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; drivers/net/forcedeth.c: if (!(np->vlanctl_bits & NVREG_VLANCONTROL_ENABLE)) drivers/net/forcedeth.c: np->txrxctl_bits &= ~NVREG_TXRXCTL_RXCHECK; drivers/net/forcedeth.c: writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); drivers/net/forcedeth.c: writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); drivers/net/forcedeth.c: nv_enable_hw_interrupts(dev, NVREG_IRQ_TIMER); drivers/net/forcedeth.c: nv_disable_hw_interrupts(dev, NVREG_IRQ_TIMER); drivers/net/forcedeth.c: writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); drivers/net/forcedeth.c: writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); drivers/net/forcedeth.c: writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); drivers/net/forcedeth.c: writel(NVREG_MISC1_FORCE, base + NvRegMisc1); drivers/net/forcedeth.c: writel(NVREG_PFF_ALWAYS | NVREG_PFF_LOOPBACK, base + NvRegPacketFilterFlags); drivers/net/forcedeth.c: writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), drivers/net/forcedeth.c: writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); drivers/net/forcedeth.c: writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); drivers/net/forcedeth.c: writel(NVREG_IRQSTAT_MASK, base + NvRegMSIXIrqStatus); drivers/net/forcedeth.c: writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), drivers/net/forcedeth.c: writel(NVREG_TXRXCTL_KICK|np->txrxctl_bits, get_hwbase(dev) + NvRegTxRxControl); drivers/net/forcedeth.c: np->txrxctl_bits |= NVREG_TXRXCTL_VLANSTRIP | NVREG_TXRXCTL_VLANINS; drivers/net/forcedeth.c: np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANSTRIP; drivers/net/forcedeth.c: np->txrxctl_bits &= ~NVREG_TXRXCTL_VLANINS; drivers/net/forcedeth.c: mgmt_sema = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_SEMA_MASK; drivers/net/forcedeth.c: if (mgmt_sema == NVREG_XMITCTL_MGMT_SEMA_FREE) drivers/net/forcedeth.c: if (mgmt_sema != NVREG_XMITCTL_MGMT_SEMA_FREE) drivers/net/forcedeth.c: tx_ctrl |= NVREG_XMITCTL_HOST_SEMA_ACQ; drivers/net/forcedeth.c: if (((tx_ctrl & NVREG_XMITCTL_HOST_SEMA_MASK) == NVREG_XMITCTL_HOST_SEMA_ACQ) && drivers/net/forcedeth.c: ((tx_ctrl & NVREG_XMITCTL_MGMT_SEMA_MASK) == NVREG_XMITCTL_MGMT_SEMA_FREE)) drivers/net/forcedeth.c: writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); drivers/net/forcedeth.c: writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA); drivers/net/forcedeth.c: writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB); drivers/net/forcedeth.c: writel(NVREG_TX_PAUSEFRAME_DISABLE, base + NvRegTxPauseFrame); drivers/net/forcedeth.c: writel(readl(base + NvRegTransmitPoll) & NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); drivers/net/forcedeth.c: writel( ((np->rx_ring_size-1) << NVREG_RINGSZ_RXSHIFT) + ((np->tx_ring_size-1) << NVREG_RINGSZ_TXSHIFT), drivers/net/forcedeth.c: writel(NVREG_TX_WM_DESC1_DEFAULT, base + NvRegTxWatermark); drivers/net/forcedeth.c: writel(NVREG_TX_WM_DESC2_3_DEFAULT, base + NvRegTxWatermark); drivers/net/forcedeth.c: writel(NVREG_TXRXCTL_BIT1|np->txrxctl_bits, base + NvRegTxRxControl); drivers/net/forcedeth.c: reg_delay(dev, NvRegUnknownSetupReg5, NVREG_UNKSETUP5_BIT31, NVREG_UNKSETUP5_BIT31, drivers/net/forcedeth.c: writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); drivers/net/forcedeth.c: writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); drivers/net/forcedeth.c: writel(NVREG_MISC1_FORCE | NVREG_MISC1_HD, base + NvRegMisc1); drivers/net/forcedeth.c: writel(NVREG_PFF_ALWAYS, base + NvRegPacketFilterFlags); drivers/net/forcedeth.c: writel(NVREG_RNDSEED_FORCE | (i&NVREG_RNDSEED_MASK), base + NvRegRandomSeed); drivers/net/forcedeth.c: writel(NVREG_TX_DEFERRAL_DEFAULT, base + NvRegTxDeferral); drivers/net/forcedeth.c: writel(NVREG_RX_DEFERRAL_DEFAULT, base + NvRegRxDeferral); drivers/net/forcedeth.c: writel(NVREG_POLL_DEFAULT_THROUGHPUT, base + NvRegPollingInterval); drivers/net/forcedeth.c: writel(NVREG_POLL_DEFAULT_CPU, base + NvRegPollingInterval); drivers/net/forcedeth.c: writel(NVREG_UNKSETUP6_VAL, base + NvRegUnknownSetupReg6); drivers/net/forcedeth.c: writel((np->phyaddr << NVREG_ADAPTCTL_PHYSHIFT)|NVREG_ADAPTCTL_PHYVALID|NVREG_ADAPTCTL_RUNNING, drivers/net/forcedeth.c: writel(NVREG_MIISPEED_BIT8|NVREG_MIIDELAY, base + NvRegMIISpeed); drivers/net/forcedeth.c: writel(NVREG_MII_LINKCHANGE, base + NvRegMIIMask); drivers/net/forcedeth.c: writel(NVREG_WAKEUPFLAGS_ENABLE , base + NvRegWakeUpFlags); drivers/net/forcedeth.c: if ( (i & NVREG_POWERSTATE_POWEREDUP) == 0) drivers/net/forcedeth.c: writel(NVREG_POWERSTATE_POWEREDUP|i, base + NvRegPowerState); drivers/net/forcedeth.c: writel(readl(base + NvRegPowerState) | NVREG_POWERSTATE_VALID, base + NvRegPowerState); drivers/net/forcedeth.c: writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); drivers/net/forcedeth.c: writel(NVREG_IRQSTAT_MASK, base + NvRegIrqStatus); drivers/net/forcedeth.c: writel(NVREG_MCASTADDRA_FORCE, base + NvRegMulticastAddrA); drivers/net/forcedeth.c: writel(NVREG_MCASTMASKA_NONE, base + NvRegMulticastMaskA); drivers/net/forcedeth.c: writel(NVREG_MCASTMASKB_NONE, base + NvRegMulticastMaskB); drivers/net/forcedeth.c: writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); drivers/net/forcedeth.c: writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); drivers/net/forcedeth.c: writel(NVREG_PFF_ALWAYS|NVREG_PFF_MYADDR, base + NvRegPacketFilterFlags); drivers/net/forcedeth.c: np->txrxctl_bits = NVREG_TXRXCTL_DESC_3; drivers/net/forcedeth.c: np->txrxctl_bits = NVREG_TXRXCTL_DESC_2; drivers/net/forcedeth.c: np->txrxctl_bits = NVREG_TXRXCTL_DESC_1; drivers/net/forcedeth.c: np->txrxctl_bits |= NVREG_TXRXCTL_RXCHECK; drivers/net/forcedeth.c: np->vlanctl_bits = NVREG_VLANCONTROL_ENABLE; drivers/net/forcedeth.c: } else if (txreg & NVREG_TRANSMITPOLL_MAC_ADDR_REV) { drivers/net/forcedeth.c: writel(txreg|NVREG_TRANSMITPOLL_MAC_ADDR_REV, base + NvRegTransmitPoll); drivers/net/forcedeth.c: powerstate &= ~NVREG_POWERSTATE2_POWERUP_MASK; drivers/net/forcedeth.c: powerstate |= NVREG_POWERSTATE2_POWERUP_REV_A3; drivers/net/forcedeth.c: np->irqmask = NVREG_IRQMASK_THROUGHPUT; drivers/net/forcedeth.c: np->irqmask = NVREG_IRQMASK_CPU; drivers/net/forcedeth.c: np->irqmask |= NVREG_IRQ_TIMER; drivers/net/forcedeth.c: if (phystate & NVREG_ADAPTCTL_RUNNING) { drivers/net/forcedeth.c: phystate &= ~NVREG_ADAPTCTL_RUNNING; drivers/net/forcedeth.c: writel(NVREG_MIISTAT_MASK_ALL, base + NvRegMIIStatus); drivers/net/forcedeth.c: if (readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_PHY_INIT) { drivers/net/forcedeth.c: np->mac_in_use = readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_MGMT_ST; drivers/net/forcedeth.c: if ((readl(base + NvRegTransmitterControl) & NVREG_XMITCTL_SYNC_MASK) == drivers/net/forcedeth.c: NVREG_XMITCTL_SYNC_PHY_INIT) { drivers/net/forcedeth.c: np->linkspeed = NVREG_LINKSPEED_FORCE|NVREG_LINKSPEED_10; drivers/net/forcedeth.c: writel(phystate|NVREG_ADAPTCTL_RUNNING, base + NvRegAdapterControl); drivers/net/forcedeth.c: writel(readl(base + NvRegTransmitPoll) & ~NVREG_TRANSMITPOLL_MAC_ADDR_REV, drivers/net/forcedeth.c: txreg |= NVREG_TRANSMITPOLL_MAC_ADDR_REV; drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL 0x000008b4 drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_2 (0xfL<<0) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_XI (0xfL<<0) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS14_XI (0L<<0) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS12_XI (1L<<0) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS10_XI (2L<<0) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS8_XI (3L<<0) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS6_XI (4L<<0) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS4_XI (5L<<0) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_PLUS2_XI (6L<<0) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_NOM_XI (7L<<0) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS2_XI (8L<<0) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS4_XI (9L<<0) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS6_XI (10L<<0) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS8_XI (11L<<0) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS10_XI (12L<<0) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS12_XI (13L<<0) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS14_XI (14L<<0) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MAIN_MINUS16_XI (15L<<0) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_2_5 (0xfL<<4) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_2_5_PLUS14 (0L<<4) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_2_5_PLUS12 (1L<<4) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_2_5_PLUS10 (2L<<4) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_2_5_PLUS8 (3L<<4) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_2_5_PLUS6 (4L<<4) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_2_5_PLUS4 (5L<<4) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_2_5_PLUS2 (6L<<4) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_2_5_NOM (7L<<4) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_2_5_MINUS2 (8L<<4) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_2_5_MINUS4 (9L<<4) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_2_5_MINUS6 (10L<<4) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_2_5_MINUS8 (11L<<4) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_2_5_MINUS10 (12L<<4) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_2_5_MINUS12 (13L<<4) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_2_5_MINUS14 (14L<<4) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_2_5_MINUS16 (15L<<4) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MGMT (0xfL<<8) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS14 (0L<<8) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS12 (1L<<8) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS10 (2L<<8) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS8 (3L<<8) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS6 (4L<<8) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS4 (5L<<8) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_PLUS2 (6L<<8) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_NOM (7L<<8) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS2 (8L<<8) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS4 (9L<<8) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS6 (10L<<8) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS8 (11L<<8) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS10 (12L<<8) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS12 (13L<<8) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS14 (14L<<8) drivers/net/bnx2.h:#define BNX2_MISC_VREG_CONTROL_1_0_MGMT_MINUS16 (15L<<8) drivers/net/bnx2.c: REG_WR(bp, BNX2_MISC_VREG_CONTROL, 0x000000fa); include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_MSMA_ID 0 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_MSMP_ID 1 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_MSME1_ID 2 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_MSMC1_ID 3 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_MSMC2_ID 4 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_GP3_ID 5 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_MSME2_ID 6 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_GP4_ID 7 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_GP1_ID 8 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_TCXO_ID 9 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_PA_ID 10 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_RFTX_ID 11 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_RFRX1_ID 12 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_RFRX2_ID 13 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_SYNT_ID 14 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_WLAN_ID 15 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_USB_ID 16 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_BOOST_ID 17 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_MMC_ID 18 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_RUIM_ID 19 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_MSMC0_ID 20 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_GP2_ID 21 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_GP5_ID 22 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_GP6_ID 23 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_RF_ID 24 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_RF_VCO_ID 26 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_MPLL_ID 27 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_S2_ID 28 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_S3_ID 29 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_RFUBM_ID 30 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_NCP_ID 31 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_ID_INVALID 32 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_MSME_ID PM_VREG_MSME1_ID include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_MSME_BUCK_SMPS_ID PM_VREG_MSME1_ID include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_MSME1_LDO_ID PM_VREG_MSME1_ID include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_MSMC_ID PM_VREG_MSMC1_ID include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_MSMC_LDO_ID PM_VREG_MSMC1_ID include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_MSMC1_BUCK_SMPS_ID PM_VREG_MSMC1_ID include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_MSME2_LDO_ID PM_VREG_MSME2_ID include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_CAM_ID PM_VREG_GP1_ID include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_MDDI_ID PM_VREG_GP2_ID include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_RUIM2_ID PM_VREG_GP3_ID include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_AUX_ID PM_VREG_GP4_ID include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_AUX2_ID PM_VREG_GP5_ID include/asm-arm/arch-msm/rpc_pm.h:#define PM_VREG_BT_ID PM_VREG_GP6_ID include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_MMC_APP__MINI_SD 1 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_MMC_APP__LCD 2 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_MMC_APP__BT 8 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_MMC_APP__MISC_SENSOR 4 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_MMC_APP__MMC 16 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_BOOST_APP__LCD 1 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_BOOST_APP__OTG 2 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_SYNTH_APP__CHAIN0 1 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_SYNTH_APP__CHAIN1 2 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_SYNTH_APP__RF_GSM 4 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_RFRX1_APP__RF_CHAIN0 1 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_RFRX1_APP__RF_CHAIN1 2 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_RFRX1_APP__GPS 4 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_RFRX1_APP__RF_GSM 8 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_RFRX2_APP__RF 1 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_RFRX2_APP__GPS 2 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_PA_APP__RF 1 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_RFTX_APP__RF 1 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_RFTX_APP__PA_THERM 2 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_RFTX_APP__RF_GSM 4 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_SYNTH_APP_GPS__CHAIN0 1 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_SYNTH_APP_GPS__CHAIN1 2 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_WLAN_APP__BT 1 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_RUIM_APP__RUIM 1 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_RUIM2_APP__CAMIF 1 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_MDDI_APP__CAMIF 1 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_CAM_APP__CAMIF 1 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_AUX_APP__AUX 1 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_AUX2_APP__AUX2 1 include/asm-arm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_BT_APP__BT 1 include/asm-arm/arch-msm/vreg.h:#ifndef __ARCH_ARM_MACH_MSM_VREG_H include/asm-arm/arch-msm/vreg.h:#define __ARCH_ARM_MACH_MSM_VREG_H include/asm-arm/arch-msm/vreg.h:struct vreg *vreg_get(struct device *dev, const char *id); include/asm-arm/arch-msm/vreg.h:void vreg_put(struct vreg *vreg); include/asm-arm/arch-msm/vreg.h:int vreg_enable(struct vreg *vreg); include/asm-arm/arch-msm/vreg.h:void vreg_disable(struct vreg *vreg); include/asm-arm/arch-msm/vreg.h:int vreg_set_level(struct vreg *vreg, unsigned mv); include/asm-arm/arch/rpc_pm.h:#define PM_VREG_MSMA_ID 0 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_MSMP_ID 1 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_MSME1_ID 2 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_MSMC1_ID 3 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_MSMC2_ID 4 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_GP3_ID 5 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_MSME2_ID 6 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_GP4_ID 7 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_GP1_ID 8 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_TCXO_ID 9 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_PA_ID 10 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_RFTX_ID 11 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_RFRX1_ID 12 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_RFRX2_ID 13 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_SYNT_ID 14 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_WLAN_ID 15 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_USB_ID 16 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_BOOST_ID 17 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_MMC_ID 18 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_RUIM_ID 19 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_MSMC0_ID 20 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_GP2_ID 21 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_GP5_ID 22 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_GP6_ID 23 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_RF_ID 24 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_RF_VCO_ID 26 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_MPLL_ID 27 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_S2_ID 28 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_S3_ID 29 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_RFUBM_ID 30 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_NCP_ID 31 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_ID_INVALID 32 include/asm-arm/arch/rpc_pm.h:#define PM_VREG_MSME_ID PM_VREG_MSME1_ID include/asm-arm/arch/rpc_pm.h:#define PM_VREG_MSME_BUCK_SMPS_ID PM_VREG_MSME1_ID include/asm-arm/arch/rpc_pm.h:#define PM_VREG_MSME1_LDO_ID PM_VREG_MSME1_ID include/asm-arm/arch/rpc_pm.h:#define PM_VREG_MSMC_ID PM_VREG_MSMC1_ID include/asm-arm/arch/rpc_pm.h:#define PM_VREG_MSMC_LDO_ID PM_VREG_MSMC1_ID include/asm-arm/arch/rpc_pm.h:#define PM_VREG_MSMC1_BUCK_SMPS_ID PM_VREG_MSMC1_ID include/asm-arm/arch/rpc_pm.h:#define PM_VREG_MSME2_LDO_ID PM_VREG_MSME2_ID include/asm-arm/arch/rpc_pm.h:#define PM_VREG_CAM_ID PM_VREG_GP1_ID include/asm-arm/arch/rpc_pm.h:#define PM_VREG_MDDI_ID PM_VREG_GP2_ID include/asm-arm/arch/rpc_pm.h:#define PM_VREG_RUIM2_ID PM_VREG_GP3_ID include/asm-arm/arch/rpc_pm.h:#define PM_VREG_AUX_ID PM_VREG_GP4_ID include/asm-arm/arch/rpc_pm.h:#define PM_VREG_AUX2_ID PM_VREG_GP5_ID include/asm-arm/arch/rpc_pm.h:#define PM_VREG_BT_ID PM_VREG_GP6_ID include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_MMC_APP__MINI_SD 1 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_MMC_APP__LCD 2 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_MMC_APP__BT 8 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_MMC_APP__MISC_SENSOR 4 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_MMC_APP__MMC 16 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_BOOST_APP__LCD 1 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_BOOST_APP__OTG 2 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_SYNTH_APP__CHAIN0 1 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_SYNTH_APP__CHAIN1 2 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_SYNTH_APP__RF_GSM 4 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_RFRX1_APP__RF_CHAIN0 1 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_RFRX1_APP__RF_CHAIN1 2 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_RFRX1_APP__GPS 4 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_RFRX1_APP__RF_GSM 8 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_RFRX2_APP__RF 1 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_RFRX2_APP__GPS 2 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_PA_APP__RF 1 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_RFTX_APP__RF 1 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_RFTX_APP__PA_THERM 2 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_RFTX_APP__RF_GSM 4 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_SYNTH_APP_GPS__CHAIN0 1 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_SYNTH_APP_GPS__CHAIN1 2 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_WLAN_APP__BT 1 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_RUIM_APP__RUIM 1 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_RUIM2_APP__CAMIF 1 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_MDDI_APP__CAMIF 1 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_CAM_APP__CAMIF 1 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_AUX_APP__AUX 1 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_AUX2_APP__AUX2 1 include/asm-arm/arch/rpc_pm.h:#define PM_VOTE_VREG_BT_APP__BT 1 include/asm-arm/arch/vreg.h:#ifndef __ARCH_ARM_MACH_MSM_VREG_H include/asm-arm/arch/vreg.h:#define __ARCH_ARM_MACH_MSM_VREG_H include/asm-arm/arch/vreg.h:struct vreg *vreg_get(struct device *dev, const char *id); include/asm-arm/arch/vreg.h:void vreg_put(struct vreg *vreg); include/asm-arm/arch/vreg.h:int vreg_enable(struct vreg *vreg); include/asm-arm/arch/vreg.h:void vreg_disable(struct vreg *vreg); include/asm-arm/arch/vreg.h:int vreg_set_level(struct vreg *vreg, unsigned mv); include/asm/arch-msm/rpc_pm.h:#define PM_VREG_MSMA_ID 0 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_MSMP_ID 1 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_MSME1_ID 2 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_MSMC1_ID 3 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_MSMC2_ID 4 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_GP3_ID 5 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_MSME2_ID 6 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_GP4_ID 7 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_GP1_ID 8 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_TCXO_ID 9 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_PA_ID 10 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_RFTX_ID 11 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_RFRX1_ID 12 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_RFRX2_ID 13 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_SYNT_ID 14 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_WLAN_ID 15 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_USB_ID 16 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_BOOST_ID 17 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_MMC_ID 18 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_RUIM_ID 19 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_MSMC0_ID 20 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_GP2_ID 21 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_GP5_ID 22 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_GP6_ID 23 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_RF_ID 24 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_RF_VCO_ID 26 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_MPLL_ID 27 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_S2_ID 28 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_S3_ID 29 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_RFUBM_ID 30 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_NCP_ID 31 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_ID_INVALID 32 include/asm/arch-msm/rpc_pm.h:#define PM_VREG_MSME_ID PM_VREG_MSME1_ID include/asm/arch-msm/rpc_pm.h:#define PM_VREG_MSME_BUCK_SMPS_ID PM_VREG_MSME1_ID include/asm/arch-msm/rpc_pm.h:#define PM_VREG_MSME1_LDO_ID PM_VREG_MSME1_ID include/asm/arch-msm/rpc_pm.h:#define PM_VREG_MSMC_ID PM_VREG_MSMC1_ID include/asm/arch-msm/rpc_pm.h:#define PM_VREG_MSMC_LDO_ID PM_VREG_MSMC1_ID include/asm/arch-msm/rpc_pm.h:#define PM_VREG_MSMC1_BUCK_SMPS_ID PM_VREG_MSMC1_ID include/asm/arch-msm/rpc_pm.h:#define PM_VREG_MSME2_LDO_ID PM_VREG_MSME2_ID include/asm/arch-msm/rpc_pm.h:#define PM_VREG_CAM_ID PM_VREG_GP1_ID include/asm/arch-msm/rpc_pm.h:#define PM_VREG_MDDI_ID PM_VREG_GP2_ID include/asm/arch-msm/rpc_pm.h:#define PM_VREG_RUIM2_ID PM_VREG_GP3_ID include/asm/arch-msm/rpc_pm.h:#define PM_VREG_AUX_ID PM_VREG_GP4_ID include/asm/arch-msm/rpc_pm.h:#define PM_VREG_AUX2_ID PM_VREG_GP5_ID include/asm/arch-msm/rpc_pm.h:#define PM_VREG_BT_ID PM_VREG_GP6_ID include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_MMC_APP__MINI_SD 1 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_MMC_APP__LCD 2 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_MMC_APP__BT 8 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_MMC_APP__MISC_SENSOR 4 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_MMC_APP__MMC 16 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_BOOST_APP__LCD 1 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_BOOST_APP__OTG 2 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_SYNTH_APP__CHAIN0 1 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_SYNTH_APP__CHAIN1 2 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_SYNTH_APP__RF_GSM 4 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_RFRX1_APP__RF_CHAIN0 1 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_RFRX1_APP__RF_CHAIN1 2 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_RFRX1_APP__GPS 4 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_RFRX1_APP__RF_GSM 8 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_RFRX2_APP__RF 1 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_RFRX2_APP__GPS 2 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_PA_APP__RF 1 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_RFTX_APP__RF 1 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_RFTX_APP__PA_THERM 2 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_RFTX_APP__RF_GSM 4 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_SYNTH_APP_GPS__CHAIN0 1 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_SYNTH_APP_GPS__CHAIN1 2 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_WLAN_APP__BT 1 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_RUIM_APP__RUIM 1 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_RUIM2_APP__CAMIF 1 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_MDDI_APP__CAMIF 1 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_CAM_APP__CAMIF 1 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_AUX_APP__AUX 1 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_AUX2_APP__AUX2 1 include/asm/arch-msm/rpc_pm.h:#define PM_VOTE_VREG_BT_APP__BT 1 include/asm/arch-msm/vreg.h:#ifndef __ARCH_ARM_MACH_MSM_VREG_H include/asm/arch-msm/vreg.h:#define __ARCH_ARM_MACH_MSM_VREG_H include/asm/arch-msm/vreg.h:struct vreg *vreg_get(struct device *dev, const char *id); include/asm/arch-msm/vreg.h:void vreg_put(struct vreg *vreg); include/asm/arch-msm/vreg.h:int vreg_enable(struct vreg *vreg); include/asm/arch-msm/vreg.h:void vreg_disable(struct vreg *vreg); include/asm/arch-msm/vreg.h:int vreg_set_level(struct vreg *vreg, unsigned mv); include/asm/arch/rpc_pm.h:#define PM_VREG_MSMA_ID 0 include/asm/arch/rpc_pm.h:#define PM_VREG_MSMP_ID 1 include/asm/arch/rpc_pm.h:#define PM_VREG_MSME1_ID 2 include/asm/arch/rpc_pm.h:#define PM_VREG_MSMC1_ID 3 include/asm/arch/rpc_pm.h:#define PM_VREG_MSMC2_ID 4 include/asm/arch/rpc_pm.h:#define PM_VREG_GP3_ID 5 include/asm/arch/rpc_pm.h:#define PM_VREG_MSME2_ID 6 include/asm/arch/rpc_pm.h:#define PM_VREG_GP4_ID 7 include/asm/arch/rpc_pm.h:#define PM_VREG_GP1_ID 8 include/asm/arch/rpc_pm.h:#define PM_VREG_TCXO_ID 9 include/asm/arch/rpc_pm.h:#define PM_VREG_PA_ID 10 include/asm/arch/rpc_pm.h:#define PM_VREG_RFTX_ID 11 include/asm/arch/rpc_pm.h:#define PM_VREG_RFRX1_ID 12 include/asm/arch/rpc_pm.h:#define PM_VREG_RFRX2_ID 13 include/asm/arch/rpc_pm.h:#define PM_VREG_SYNT_ID 14 include/asm/arch/rpc_pm.h:#define PM_VREG_WLAN_ID 15 include/asm/arch/rpc_pm.h:#define PM_VREG_USB_ID 16 include/asm/arch/rpc_pm.h:#define PM_VREG_BOOST_ID 17 include/asm/arch/rpc_pm.h:#define PM_VREG_MMC_ID 18 include/asm/arch/rpc_pm.h:#define PM_VREG_RUIM_ID 19 include/asm/arch/rpc_pm.h:#define PM_VREG_MSMC0_ID 20 include/asm/arch/rpc_pm.h:#define PM_VREG_GP2_ID 21 include/asm/arch/rpc_pm.h:#define PM_VREG_GP5_ID 22 include/asm/arch/rpc_pm.h:#define PM_VREG_GP6_ID 23 include/asm/arch/rpc_pm.h:#define PM_VREG_RF_ID 24 include/asm/arch/rpc_pm.h:#define PM_VREG_RF_VCO_ID 26 include/asm/arch/rpc_pm.h:#define PM_VREG_MPLL_ID 27 include/asm/arch/rpc_pm.h:#define PM_VREG_S2_ID 28 include/asm/arch/rpc_pm.h:#define PM_VREG_S3_ID 29 include/asm/arch/rpc_pm.h:#define PM_VREG_RFUBM_ID 30 include/asm/arch/rpc_pm.h:#define PM_VREG_NCP_ID 31 include/asm/arch/rpc_pm.h:#define PM_VREG_ID_INVALID 32 include/asm/arch/rpc_pm.h:#define PM_VREG_MSME_ID PM_VREG_MSME1_ID include/asm/arch/rpc_pm.h:#define PM_VREG_MSME_BUCK_SMPS_ID PM_VREG_MSME1_ID include/asm/arch/rpc_pm.h:#define PM_VREG_MSME1_LDO_ID PM_VREG_MSME1_ID include/asm/arch/rpc_pm.h:#define PM_VREG_MSMC_ID PM_VREG_MSMC1_ID include/asm/arch/rpc_pm.h:#define PM_VREG_MSMC_LDO_ID PM_VREG_MSMC1_ID include/asm/arch/rpc_pm.h:#define PM_VREG_MSMC1_BUCK_SMPS_ID PM_VREG_MSMC1_ID include/asm/arch/rpc_pm.h:#define PM_VREG_MSME2_LDO_ID PM_VREG_MSME2_ID include/asm/arch/rpc_pm.h:#define PM_VREG_CAM_ID PM_VREG_GP1_ID include/asm/arch/rpc_pm.h:#define PM_VREG_MDDI_ID PM_VREG_GP2_ID include/asm/arch/rpc_pm.h:#define PM_VREG_RUIM2_ID PM_VREG_GP3_ID include/asm/arch/rpc_pm.h:#define PM_VREG_AUX_ID PM_VREG_GP4_ID include/asm/arch/rpc_pm.h:#define PM_VREG_AUX2_ID PM_VREG_GP5_ID include/asm/arch/rpc_pm.h:#define PM_VREG_BT_ID PM_VREG_GP6_ID include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_MMC_APP__MINI_SD 1 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_MMC_APP__LCD 2 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_MMC_APP__BT 8 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_MMC_APP__MISC_SENSOR 4 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_MMC_APP__MMC 16 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_BOOST_APP__LCD 1 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_BOOST_APP__OTG 2 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_SYNTH_APP__CHAIN0 1 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_SYNTH_APP__CHAIN1 2 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_SYNTH_APP__RF_GSM 4 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_RFRX1_APP__RF_CHAIN0 1 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_RFRX1_APP__RF_CHAIN1 2 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_RFRX1_APP__GPS 4 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_RFRX1_APP__RF_GSM 8 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_RFRX2_APP__RF 1 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_RFRX2_APP__GPS 2 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_PA_APP__RF 1 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_RFTX_APP__RF 1 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_RFTX_APP__PA_THERM 2 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_RFTX_APP__RF_GSM 4 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_SYNTH_APP_GPS__CHAIN0 1 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_SYNTH_APP_GPS__CHAIN1 2 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_WLAN_APP__BT 1 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_RUIM_APP__RUIM 1 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_RUIM2_APP__CAMIF 1 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_MDDI_APP__CAMIF 1 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_CAM_APP__CAMIF 1 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_AUX_APP__AUX 1 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_AUX2_APP__AUX2 1 include/asm/arch/rpc_pm.h:#define PM_VOTE_VREG_BT_APP__BT 1 include/asm/arch/vreg.h:#ifndef __ARCH_ARM_MACH_MSM_VREG_H include/asm/arch/vreg.h:#define __ARCH_ARM_MACH_MSM_VREG_H include/asm/arch/vreg.h:struct vreg *vreg_get(struct device *dev, const char *id); include/asm/arch/vreg.h:void vreg_put(struct vreg *vreg); include/asm/arch/vreg.h:int vreg_enable(struct vreg *vreg); include/asm/arch/vreg.h:void vreg_disable(struct vreg *vreg); include/asm/arch/vreg.h:int vreg_set_level(struct vreg *vreg, unsigned mv); System.map:c000df94 t vreg_debug_init System.map:c001c4f4 t __initcall_vreg_debug_init6 System.map:c002bbc8 T vreg_put System.map:c002bbd8 t vreg_debug_get System.map:c002bbec t vreg_fops_open System.map:c002bc24 T vreg_set_level System.map:c002bc58 T vreg_disable System.map:c002bc90 T vreg_enable System.map:c002bcc8 t vreg_debug_set System.map:c002bd18 T vreg_get System.map:c0298ce0 d vreg_fops Binary file vmlinux matches Binary file vmlinux.o matches